The canonic sign digit (CSD) number system is both a technique for representing fixed-point numbers and an algorithm for multiplying one fixed-point number by another. Through the addition of look-up-table (LUT) based control logic, the simple CSD scaler (ie: fixed-coefficient multiplier) can be converted to a hardware-efficient full four-quadrant multiplier with applications in adaptive filters, digital up-converters and down-converters, Two novel circuits are designed to take advantage of the Xilinx FPGA architecture to provide simple, yet hardware-efficient multipliers. The multipliers are designed for application in adaptive digital filters, Fourier transforms, and other DSP applications that require an efficient four-quadrant multiplier.