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High performance asynchronous bus for SoC | IEEE Conference Publication | IEEE Xplore

High performance asynchronous bus for SoC


Abstract:

It is difficult to use synchronous buses in a system-on-a-chip design due to the increase of wire delay caused by the crosstalk effect and the difficulty of the synchroni...Show More

Abstract:

It is difficult to use synchronous buses in a system-on-a-chip design due to the increase of wire delay caused by the crosstalk effect and the difficulty of the synchronization caused by the clock-skew problem. The use of an asynchronous bus is an alternative solution for the SoC design method. In this paper, we propose a new high performance asynchronous bus using a return-to-zero data encoding method to get a low latency and a high throughput as well. Simulation results reveal that, by the proposed scheme, the read throughput increases by 17.6%, and the read latency decreases by 12.5% simultaneously.
Date of Conference: 25-28 May 2003
Date Added to IEEE Xplore: 20 June 2003
Print ISBN:0-7803-7761-3
Conference Location: Bangkok, Thailand

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