By using a polynomial basis with LSB (Least Significant Bit) first scheme, we present new bit serial and bit parallel systolic multipliers over GF(2/sup m/). Our bit serial systolic multiplier has only one control signal with 10 latches in each basic cell. Also, our bit parallel multiplier has unidirectional data flow with 7 latches in each basic cell. Thus, whether it is bit serial or bit parallel, our multiplier has a better or comparable hardware complexity and critical path delay and has the same unidirectional data flow to the multipliers with MSB (Most Significant Bit) first scheme.