This paper presents the behavioral simulation of a fourth-order multi-bit continuous-time bandpass /spl Delta/-/spl Sigma/ analog-to-digital converter (ADC) for direct radio frequency (RF) conversion in multi-band 3G base stations. With a 2.1 GHz carrier frequency, the conventional method requires a sampling frequency greater than 8 GHz. To overcome the design complexity, jitter issue, and high power consumption anticipated for a design at such a high sampling-rate, we propose a new mirrored-image sampling technique to achieve targeted ADC performance at a much lower sampling rate. Detailed analysis of stability and signal-to-noise ratio (SNR) find the optimum DAC topology and design parameters. With an RZ33%-DAC, the ADC is capable of digitizing a 2.1 GHz RF signal with a 20 MHz band at 2.8 Gsamples/sec, and achieving a 87 dB SNR.