An input-free NMOS V/sub T/ (threshold voltage) extractor circuit in an n-well CMOS process is presented. The non-idealities due to NMOS body effects on the extracted V/sub T/ are automatically compensated in the circuit. PMOS difference amplifiers are developed to compute the difference of node voltages such that the V/sub T/ of the NMOS device can be extracted as a voltage, referenced to ground or VDD. The proposed NMOS V/sub 2/ extractor circuit was fabricated in a 0.25 /spl mu/m CMOS process, and the extracted V/sub T/, which had an absolute value of 0.441V, had an accuracy of 95.7%.