This paper presents an iterated short convolution (ISC) algorithm, based on the mixed radix algorithm and fast convolution algorithm. This ISC based linear convolution structure is transposed to obtain a new hardware efficient fast parallel FIR filter structure, which save a lot of amount of hardware cost, especially when the length of the FIR filter is large. For example, for a 576-tap filter, the proposed structure saves 16.7% to 43.6% of the delay elements and 2.9% to 27% of the additions, which prior fast parallel structures use, when the level of parallelism varies from 6 to 72. These proposed structures exhibit regular structure.