A zero-forcing equalizer, based on the Laguerre filter architecture is proposed. The equalizer is designed using the residues and poles of the estimated transfer function that is required to be inverted. The paper describes the equalizer filter design procedure in detail. The advantage of using the Laguerre architecture in FPGA type hardware implementation is elaborated. The designed zero-forcing Laguerre equalizer could be extended for other type of equalizers such as adaptive equalizers and decision feed-back equalizers. An example of the Laguerre residue equalizer is shown in a communication application.