The decomposition of the multiplication of a variable by a set of constants into a multiplierless shift-and-add block has been a core operation and often performance bottleneck in many DSP applications. In this paper, a new contention resolution algorithm (CRA), based on an ingenious graph synthesis approach has been developed for the common subexpression elimination of the multiplier block of digital filter structure. The algorithm, CRA manages two-bit common subexpressions with the primary goal to achieve minimal logic depth. The performances of CRA are analyzed and evaluated. The results demonstrated that CRA outperforms many distinguished algorithms in logic depth and where algorithms in comparison have compatible logic depth, CRA has lower logic complexity.