In this paper, reusable intellectual property cores for the efficient implementation of digital signal processing (DSP) applications such as wireless LAN are presented. More specifically, a split-radix FFT algorithm implementation architecture, whose applicability for these communication systems has been proven, was designed using reusable VHDL. Four different implementations of the split-radix butterfly element are presented. These different butterfly elements allow tradeoffs between performance, power consumption and hardware complexity. Finally, for demonstration purpose, comparison results of split-radix and radix-4 implementations on Virtex and Virtex-II devices are also presented.