This paper presents a power-aware IP core generator for the 1D DFT design. We optimize the proposed DFT IP design both in algorithm and architecture levels for achieving low hardware complexity. In algorithm level, we first use radix-2/sup c/ algorithm to split a length-N DFT into multiple length-N/2/sup c/ DFTs for facilitating computation sharing between parallel DFT outputs. Then, we formulate the length-N/2/sup c/ DFT into cyclic convolution form to facilitate the hardware cost reduction. In architecture level, we implement the design with a filter-based architecture optimized by a bit-level sub-expression sharing. In addition, we have applied the power-aware design concept in the proposed IP core generator through trading off the power consumption, data precision, and hardware cost in the design phase by parameter configurations through graphic user interface.