A reconfigurable angle rotator architecture is proposed and incorporated into an energy-efficient reconfigurable FFT/IFFT processor IC as its major computation component, endowing the FFT/IFFT processor with a significant scalable power dissipation feature with varying FFT size. The reconfigurability of the angle rotator is realized by dynamically allocating computation resources, which are subrotation stages in cascade. This approach tends to minimize the size of the lookup table while maintaining computation accuracy, and tends to minimize the area and power consumption while improving the overall performance.