Design strategies for PFSCL (positive feedback source-coupled logic) gates are discussed. Criteria to size transistor aspect ratios and bias currents are derived as a function of the requirements on the noise margin and the power-delay trade-off, which are analytically modeled. The design criteria are also discussed in cases which are of practical interest, i.e., when a high speed or an optimum balance with power dissipation is required. The proposed design strategies are simple enough to be used in pencil-and-paper calculations. The theoretical results are validated through simulations on a 0.18-/spl mu/m CMOS process.