A cascade 3-1-1 multibit /spl Sigma//spl Delta/ A/D modulator with reduced sensitivity to non-idealities | IEEE Conference Publication | IEEE Xplore

A cascade 3-1-1 multibit /spl Sigma//spl Delta/ A/D modulator with reduced sensitivity to non-idealities


Abstract:

A new 3(5b)-1(1b)-1(5b) fifth-order cascade multibit MA A/D modulator is proposed to achieve high dynamic range at low oversampling ratio of 8. The /spl Sigma//spl Delta/...Show More

Abstract:

A new 3(5b)-1(1b)-1(5b) fifth-order cascade multibit MA A/D modulator is proposed to achieve high dynamic range at low oversampling ratio of 8. The /spl Sigma//spl Delta/ modulator in the first stage accomplishes a modified 3rd-order FIR noise-transfer-function, which is stable by using a 5-bit quantizer. Moreover, low-distortion topology in this stage is employed to reduce the nonlinear effects of operational amplifiers. The second and third stages consist of the common first-order architecture with 1-bit and 5-bit quantizer, respectively. The performance of the proposed modulator is analyzed and compared with other topologies. Simulation results show that the in-band noise, especially at high frequencies, can be significantly suppressed by these arrangements and this architecture has also very low sensitivity to nonidealities of analog circuits. It is very suitable for high-resolution broadband applications, as well as for low-power design in scaled IC technologies.
Date of Conference: 23-26 May 2005
Date Added to IEEE Xplore: 25 July 2005
Print ISBN:0-7803-8834-8

ISSN Information:

Conference Location: Kobe, Japan

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