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A very-high-speed low-power low-voltage fully differential CMOS sample-and-hold circuit with low hold pedestal | IEEE Conference Publication | IEEE Xplore

A very-high-speed low-power low-voltage fully differential CMOS sample-and-hold circuit with low hold pedestal


Abstract:

A new technique for realizing a very-high-speed low-power low-voltage fully differential CMOS sample-and-hold circuit with low hold pedestal is presented. The fully diffe...Show More

Abstract:

A new technique for realizing a very-high-speed low-power low-voltage fully differential CMOS sample-and-hold circuit with low hold pedestal is presented. The fully differential double-sampled design relaxes the trade-off between sampling speed and the sampling precision. Simulation results are given to demonstrate the potential advantage of the new technique.
Date of Conference: 23-26 May 2005
Date Added to IEEE Xplore: 25 July 2005
Print ISBN:0-7803-8834-8

ISSN Information:

Conference Location: Kobe, Japan

References

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