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Novel instructions and their hardware architecture for video signal processing | IEEE Conference Publication | IEEE Xplore

Novel instructions and their hardware architecture for video signal processing


Abstract:

H.264/AVC adopts new features compared with previous multimedia algorithms. It is inefficient to implement some of the new blocks using existing DSP instructions. Hence, ...Show More

Abstract:

H.264/AVC adopts new features compared with previous multimedia algorithms. It is inefficient to implement some of the new blocks using existing DSP instructions. Hence, new instructions are required to implement H.264/AVC. This paper proposes novel instructions for intra-prediction, in-loop deblocking filter, entropy coding and integer transform. Performance comparisons show that the required computation cycles for the in-loop deblocking filter can be reduced by about 20/spl sim/25%. This paper also proposes new instructions for the integer transform. The proposed instructions can execute the 1D forward/inverse integer transform. The integer transform can be implemented using much smaller hardware size than existing DSPs.
Date of Conference: 23-26 May 2005
Date Added to IEEE Xplore: 25 July 2005
Print ISBN:0-7803-8834-8

ISSN Information:

Conference Location: Kobe, Japan

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