Loading [a11y]/accessibility-menu.js
A ns-2 simulator utilizing chaotic maps for network-on-chip traffic analysis | IEEE Conference Publication | IEEE Xplore

A ns-2 simulator utilizing chaotic maps for network-on-chip traffic analysis


Abstract:

NoC (network-on-chip) is an emerging paradigm that copes with the increasing complexity and communication requirements of current SoCs (system-on-chip). We present an ns-...Show More

Abstract:

NoC (network-on-chip) is an emerging paradigm that copes with the increasing complexity and communication requirements of current SoCs (system-on-chip). We present an ns-2 (network simulator) simulation environment for NoC traffic analysis. Namely, the NoC model is illustrated in detail and simulation results are reported. One-dimensional chaotic maps are used for generating long-range dependent traffic.
Date of Conference: 23-26 May 2005
Date Added to IEEE Xplore: 25 July 2005
Print ISBN:0-7803-8834-8

ISSN Information:

Conference Location: Kobe, Japan

Contact IEEE to Subscribe

References

References is not available for this document.