This work presents two techniques for sensitizing the RF loopback path for an integrated transceiver under SER test. The test aims at spot defects typical of the CMOS process. At the chip level the spot defects are represented by impairments in gain and/or noise figure. The sensitization is based on SNR control of the test stimulus or on using a tuned interferer. In both cases power level control is crucial. The discussion is supported by simulation experiments.