Circuit-level power efficiency investigation of advanced DSP architectures based on a specialized power modeling technique | IEEE Conference Publication | IEEE Xplore

Circuit-level power efficiency investigation of advanced DSP architectures based on a specialized power modeling technique

Publisher: IEEE

Abstract:

This work presents an analysis of power efficiency in microprocessor architectures targeting wide-range digital signal processing (DSP) applications. We defined a circuit...View more

Abstract:

This work presents an analysis of power efficiency in microprocessor architectures targeting wide-range digital signal processing (DSP) applications. We defined a circuit level power estimation technique based on the integration of traditional analytical power models so as to account for both block-internal and interconnects-dependent dissipation and we extended it to provide applicability to specific DSP-related structures. We applied the modeling approach to several architecture schemes and demonstrated that a relatively novel solution, namely the transfer triggered architecture, can be the most power-efficient scheme in DSP applications.
Date of Conference: 23-26 May 2005
Date Added to IEEE Xplore: 25 July 2005
Print ISBN:0-7803-8834-8

ISSN Information:

Publisher: IEEE
Conference Location: Kobe, Japan

References

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