An RF on-chip filter using a Q-enhanced LC filter with digitally synchronized gain, center frequency (f0), and quality factor (Q) tuning is implemented in a standard 0.18 /spl mu/m CMOS process. The circuit consists of a new high-speed, wide-range, low-distortion, constant-gm OTA design and a new constant tunable discrete capacitor design that maximizes the linearity. The concept is illustrated through the design of a front-end RF filter operating at an f0 of 5.775 GHz. Simulation results show that the filtering Q can be digitally tuned from 6 to 65 while maintaining an f0 shifting within +-0.2%, gain variation 0.03 dB, 1-dB compression point (P/sub 1dB/) from -0.9 to 2.69 dBm, and dynamic range from 57 to 80 dB over the 100 MHz passband.