A 372 ps 64-bit adder using fast pull-up logic in 0.18-/spl mu/m CMOS | IEEE Conference Publication | IEEE Xplore
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A 372 ps 64-bit adder using fast pull-up logic in 0.18-/spl mu/m CMOS

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Jooyoung Kim; Kangmin Lee; Hoi-Jun Yoo
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Abstract:

This paper presents a 372 ps 64-bit adder using fast pull-up logic (FPL) in 0.18 mum CMOS technology. Fast pull-up logic is devised and applied to decrease pull-up time w...Show More

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Abstract:

This paper presents a 372 ps 64-bit adder using fast pull-up logic (FPL) in 0.18 mum CMOS technology. Fast pull-up logic is devised and applied to decrease pull-up time which is critical in domino-static adder. The implemented adder measures the worst case delay of 372 ps. The adder has a modified tree architecture using load distribution method and has 6 logic stages
Published in: 2006 IEEE International Symposium on Circuits and Systems (ISCAS)
Date of Conference: 21-24 May 2006
Date Added to IEEE Xplore: 11 September 2006
Print ISBN:0-7803-9389-9

ISSN Information:

DOI: 10.1109/ISCAS.2006.1692510
Conference Location: Island of Kos
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