Inverting closed-loop amplifier architecture with reduced gain error and high input impedance | IEEE Conference Publication | IEEE Xplore

Inverting closed-loop amplifier architecture with reduced gain error and high input impedance


Abstract:

We propose an inverting closed-loop amplifier architecture providing high input impedance and a theoretically zero gain error, without requiring infinitely large loop gai...Show More

Abstract:

We propose an inverting closed-loop amplifier architecture providing high input impedance and a theoretically zero gain error, without requiring infinitely large loop gain. The architecture is based on two nested amplifiers closed in feedback through a resistive network. A straightforward CMOS implementation is also given. Simulations using a 0.35-mum CMOS process are found in agreement with expected results. Monte Carlo simulations have also shown the robustness of the proposed approach against process tolerances
Date of Conference: 21-24 May 2006
Date Added to IEEE Xplore: 11 September 2006
Print ISBN:0-7803-9389-9

ISSN Information:

Conference Location: Kos, Greece

Contact IEEE to Subscribe

References

References is not available for this document.