The paper presents a current-mode CMOS image sensor embedded smooth spatial filter algorithm. The sensor includes a 66/spl times/66 pixel array with an on-chip 6-bit analog-to-digital converter that can identify the output value of pixels in gray level resolution. The last row of pixel cells (1/spl times/66) based on the double sampling is used for reducing fixed pattern noise (FPN). Processing circuits are dedicated for the spatial filter algorithm and support reusability to increase the image processing speed and to reduce the design complexity and chip area. The sensor chip has been designed and implemented in TSMC 0.35/spl mu/m 2P4M CMOS mixed-mode process. Each pixel occupies a area of 15.8/spl mu/m/spl times/10.6/spl mu/m with a fill factor of 37.2%. The power consumption is 35.15mW when the sensor operates at 175 frames/second.