In this paper a hardware architecture for the implementation of the flexible triangle search algorithm (FTS) using FPGAs is proposed. The FTS is a fast block-matching algorithm for motion estimation proposed in previous work, which can be used for video compression. The FTS finds the best matching blocks between two frames using a search triangle which changes its direction and size through a set of operations. These operations provide the triangle with the necessary flexibility to locate the best matching block. Simulation results indicate that the FTS reduces the number of block matching operations compared with other fast block matching algorithms without affecting quality or compression ratio of the compressed bitstream. In this paper, a hardware architecture for a FPGA implementation of the FTS algorithm is proposed. This architecture is simulated and tested using VHDL and synthesized using Xilinx ISE for the Xilinx Spartan3 device. The results obtained were compared to an FPGA implementation of the full search (FS) algorithm. Results indicates that the FTS FPGA implementation requires less number of gates than FS and the required number of cycles needed to complete motion search for one block is much lower. This indicates that the proposed implementation is fast and requires less hardware and power than existing ones.