SRAM arrays using differential sensing (DS) and single-ended sensing (SE) are designed and fabricated in a test chip and their power and performance behaviors are studied in this paper. Sense amplifier offset (DC condition), which is one of the main criterion to determine the required bit-line differential, is measured. A novel SE scheme is proposed to overcome the delay degradation due to large bit line leakage in scaled technology. With marginal switching power savings, the SE array is 56% slower than the DS array in 90 nm technology with a single high-Vt at 350 mV. The difference narrows down to 30% in low-Vt case. Using asymmetric cells, instead of symmetric cells, in single-ended large signal arrays improves delay by 3%, while the power consumption remains approximately the same.