Fast evaluation of analog circuit structures by polytopal approximations | IEEE Conference Publication | IEEE Xplore

Fast evaluation of analog circuit structures by polytopal approximations


Abstract:

In this paper we present a method for the fast evaluation of circuit structures. It is part of a methodology for the structural synthesis of analog circuits which generat...Show More

Abstract:

In this paper we present a method for the fast evaluation of circuit structures. It is part of a methodology for the structural synthesis of analog circuits which generates a large number of different circuit structures. Goal of the presented methods is to find circuit structures, which fit best the design goals. Based on implicit analog circuit specifications, as well as explicit performance specifications given by the designer, the presented method approximates the feasible region of parameters by a polytope. This polytopal approximation of the performance capabilities can be calculated and visualized or the feasibility of the specification can be tested by linear programming. The method has been validated on a set of operational amplifier structures
Date of Conference: 21-24 May 2006
Date Added to IEEE Xplore: 11 September 2006
Print ISBN:0-7803-9389-9

ISSN Information:

Conference Location: Kos, Greece

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