Noise coupling mechanism analysis is done for a successive approximation (SAR) type ADC. In the light of this, a simple redundant SAR architecture is presented that nulls conversion phase noise; non-ideal circuit behavior and is compared with the reported work which, in most cases, optimize for conversion speed alone. The 12-bit multi-channel non-calibrating charge re-distribution type SAR-ADC integrated with a large system-on-a-chip is fabricated as a test-chip and a fully integrated device in 130 nm 5 metal 1 poly CMOS "digital" process. Test-chip results show no observable degradations when switching noise was restricted to the conversion phase alone while it shows 3db SNR degradation otherwise. Though designed for 200KSPS settling time, silicon results illustrates maximum operation at 2MSPS using margins actually designed for noise. On the final integrated version, 11.4 bit ENOB and 71.5 db SNR was recorded in the presence of digital switching substrate noise/IO switching noise and board ground noises