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A new bulk-driven input stage design for sub 1-volt CMOS op-amps | IEEE Conference Publication | IEEE Xplore

A new bulk-driven input stage design for sub 1-volt CMOS op-amps


Abstract:

This paper presents a new design approach for a rail-to-rail bulk-driven input stage using a standard single-well (n-well in this paper) CMOS technology. This input stage...Show More

Abstract:

This paper presents a new design approach for a rail-to-rail bulk-driven input stage using a standard single-well (n-well in this paper) CMOS technology. This input stage can provide nearly constant transconductance and constant slew rate over the entire input common-mode voltage, operating with a wide supply voltage ranging from sub 1-volt (VT0+ 3VDSsat) to the maximum allowed for the CMOS process, as well as preventing latch-up
Date of Conference: 21-24 May 2006
Date Added to IEEE Xplore: 11 September 2006
Print ISBN:0-7803-9389-9

ISSN Information:

Conference Location: Kos, Greece

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