Power reduction has become a serious issue in recent years. In this paper, a power-efficient architecture for EBCOT tier-1 is proposed. EBCOT tier-1 architecture is divided into BC (bit-plane coding), AE (arithmetic encoding), and FIFO that connects BC with AE and balances the different throughput between them. In BC, simple control logics are added to reduce computation in bit-plane coding; in FIFO, memory access is reduced since AE is fed with fixed values instead of reading from FIFO; in AE, simple control logics are added to reduce computation in AE and forwarding technique combined with clock gating is adopted to reduce switching activities in the last two pipeline stages. Experimental results, with standard test image benchmarks, show that the proposed power reduction techniques keep the same system throughput and achieve about 48%, 16%, and 20% improvement for BC, FIFO, and AE, respectively, in the power consumption by comparison with the original architecture.