Abstract:
In a 0.13 /spl mu/m design environment, we design two level converters to convert signals from 0.6V and 0.8V to 1.2V, respectively, to fulfill the needs of a multi-island...Show MoreMetadata
Abstract:
In a 0.13 /spl mu/m design environment, we design two level converters to convert signals from 0.6V and 0.8V to 1.2V, respectively, to fulfill the needs of a multi-island dual-VDD CMOS SOC. Heuristic sizing guidelines are proposed to achieve better conversion speed and lower conversion energy for both level converters.
Date of Conference: 21-24 May 2006
Date Added to IEEE Xplore: 11 September 2006
Print ISBN:0-7803-9389-9
Contents 