Clock uncertainty is a major concern in current high performance clock network design. A differential clocking scheme provides noise immunity and can address this challenge. In this paper, a differential line equivalent delay model is proposed to obtain zero skew differential clock networks. The method is applied to various benchmarks. On average, 97% skew reduction is obtained compared to the solution derived with the classic Elmore model. To improve performance of zero skew differential clock networks, differential buffers based on dynamic threshold transistors are proposed. Incorporation of proposed buffers to low swing zero skew differential clock network shows 25% delay improvement compared to conventional buffers. Moreover, the incorporation of proposed design methods shows 25% and 6% skew variations reduction in presence of power supply variations and crosstalk noise respectively, compared to low swing single-node clock distribution networks.