In this paper, a static random access memory (SRAM) cell that reduces the gate leakage power with low access latency is proposed. The technique reduces the gate leakage current both in the zero and in the one states. The efficiency of the design is evaluated by simulating the circuit in a 45-nm CMOS technology. Compared to the conventional SRAM cell, the proposed design reduces the total gate leakage current around 58% for an oxide thickness of 1.4nm. The increase in the area of the proposed cell is minimal compared to the conventional SRAM. The read access time of this SRAM is only 5.6% slower than that of the conventional SRAM.