This paper describes a sampled analog architecture for computing 2D DCT of an 8 /spl times/ 8 image block using switched capacitor principle, with capacitance switching. The input sample stream is applied to a bank of capacitors and multiplied by all the deduced 2D DCT coefficients simultaneously using capacitor ratios. These capacitors are switched concurrently with the help of a switching matrix, to realize switched capacitor integrators for performing necessary addition/subtraction. The complexities of the circuitous two-step 2D DCT involving two separate 1D DCTs have been removed. Proposed architecture is regular, flexible and can be used as building block for real-time image and video compression, with the same accuracy as its digital counterpart.