In this paper we present our work on variation-tolerant current source design. The three-transistor-plus-resistor circuit we present, offers more than 2times reduction in standard deviation of the output current at reduced circuit complexity (in a 0.18mum technology). Moreover, our circuit can be used to mirror a reference current at various locations on the die without incurring mismatches due to process variations while requiring minimum voltage headroom and layout area. The circuit topology itself is derived from a formal methodology presented here