In this paper, a new frac14 rate clock linear phase detector (PD) structure for PLL-based clock and data recovery (CDR) circuits is suggested. The proposed topology offers a more suitable PD for high speed applications compared to the conventional topologies. The effect of duty cycle variation on the operation of CDR has been also studied. Designed in a 0.18mum CMOS technology, the proposed PD consumes 16mA from a 1.8V voltage supply