A systolic VLSI architecture is developed for a sequential Monte Carlo (SMC) receiver that performs joint channel estimation and data detection. The architecture exploits the parallelism intrinsic to the algorithm. The SMC receiver consists of the SMC core, weight calculator, and sampler. Hardware efficient architectures for each functional block are proposed. Detailed features of various mappings of the proposed VLSI architecture for the SMC core are studied. Performance analyzes at both the architecture level and system level, are also presented