This paper presents a compact self-biased current-mode filter (CMF) PLL architecture, which uses relative ratio of charge-pump currents (I_cp2 / |I_cp2-I_cp1|) to obtain a capacitor multiplier. Compatible with self-biased CMF, a modified charge pump switches structure is proposed to reduce phase offset and current activating time. The whole PLL has been designed and implemented in a 0.25 mum CMOS process. The simulated PLL provides the loop parameters almost independent of divider multiplication factor, and decreases the capacitance to 1/10 of conventional one, and the results also shows it reduces the acquisition time by a factor of about 3