Abstract:
We present the design of a flash memory for passive RFID transponders, implemented in a standard - single poly - 0.35 mum CMOS process. The memory has 128 bits, sufficien...Show MoreMetadata
Abstract:
We present the design of a flash memory for passive RFID transponders, implemented in a standard - single poly - 0.35 mum CMOS process. The memory has 128 bits, sufficient for example to contain the EPC code for Class 0 tags, and is able to perform a complete read operation of all 128 bits with an access time of about 10 ms and a power consumption of only 160 nW. In the erase/program mode Fowler-Nordheim tunneling is used, and all 128 bits can be written in 0.8 s with a power consumption of about 3 muW. Such power causes an acceptable reduction of the operating range during a write operation to 1.74 m in the 2.45 GHz ISM band and 4.66 m in the UHF ISM band, for a transmitter EIRP of 500 mW, with respect to the read operating range, where 4 m at 2.45 GHz and 10.5 m at 916 MHz are achieved
Date of Conference: 21-24 May 2006
Date Added to IEEE Xplore: 11 September 2006
Print ISBN:0-7803-9389-9