A 1.056 GS/s, 5-bit/6-bit switchable flash analog-to-digital converter (ADC) is designed in 0.18-/spl mu/m CMOS, which is suitable to be used in an OFDM-UWB transceiver. A resolution switchable structure is proposed to optimize power consumption according to the dynamic requirement of the application. Two-stage interpolation and averaging techniques are employed to average the offset of the preamplifiers. Monte Carlo simulation results show that the proposed ADC achieves 4.2b/5.0b ENOB in 5-bit/6-bit working modes with a 413-MHz input signal. The mean value of DNL and INL is 0.32 and 0.56 LSB for 5-bit mode, while 0.47 and 0.62 LSB for 6-bit mode. The analog part consumes 36 mW and 98 mW from a 1.8-V supply in 5-bit and 6-bit operation mode, respectively.