This paper is focused on low voltage, ultra low power LNA design at 404 MHz for a wireless transceiver used in a cochlear implant device. The design is implemented in a 0.18mum RF CMOS process. The circuit operated with 1V, reduced power supply voltage. The LNA performance is investigated for different power consumption levels to come up with the best performance at minimum possible power level. The performance target is, having a moderate gain and a moderate noise figure without degrading the linearity too much. The circuit, which will be used in receiver chain, consumes only 500 muW power. It has simulated noise figure of 0.9 dB, input 1-dB compression point of -19.5 dBm, input third order intercept point of -5.01 dBm and small signal gain of 15.85 dB. The design will be used in the MICS transceiver