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Single-chip FPGA architecture for 3D IIR broadband spatio-temporal beam plane-wave filters | IEEE Conference Publication | IEEE Xplore

Single-chip FPGA architecture for 3D IIR broadband spatio-temporal beam plane-wave filters


Abstract:

A highly-directional FPGA-based broadband beam former is proposed using a novel 3D IIR plane-wave digital filter. This filter acquires the 3D spatio-temporal input signal...Show More

Abstract:

A highly-directional FPGA-based broadband beam former is proposed using a novel 3D IIR plane-wave digital filter. This filter acquires the 3D spatio-temporal input signals from spatially-rectangular arrays of sensors that are scanned by only one time-multiplexed A/D converter. The proposed architecture employs a novel scanned-array 3D parallel vector-processor (VP), clocked at 80 MHz, and has the potential to achieve real-time broadband plane-wave filtering on a single low-cost integrated circuit at spatial frame-rates of 19 kHz over a 64 by 64 spatial broadband sensor array.
Date of Conference: 21-24 May 2006
Date Added to IEEE Xplore: 11 September 2006
Print ISBN:0-7803-9389-9

ISSN Information:

Conference Location: Kos, Greece

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