A simulation-equation-based methodology for designing high-performance opamps is presented. Using an iterative interface between equation analyzer and circuit simulator, ISECAD an automatic computer-aided-design (CAD) is developed to design high-performance two-stage cascode-compensated opamp in deep-sub-micron technologies. The sizes of all devices are optimally determined in the circuit with specific structure. A sample opamp is designed employing this CAD for 1.8-V supply voltage in 0.18-/spl mu/m CMOS technology. Simulations show that the opamp achieves 79dB DC gain, 323MHz unity-gain frequency and 50/spl deg/ phase margin.