Abstract:
This paper proposes a flexible architecture of the transform processor for multi-CODECs (JPEG, MPEG-2, 4 and H.264). Also the memory control scheme to efficiently store i...Show MoreMetadata
Abstract:
This paper proposes a flexible architecture of the transform processor for multi-CODECs (JPEG, MPEG-2, 4 and H.264). Also the memory control scheme to efficiently store intermediate data is presented. In the proposed architecture, four arrays block process at the same time with 4 parallel process elements and pipelined structure for improving the processing time. For verification, FPGA platform with ARM-9 core is used. The results show that the proposed architecture satisfies the requirements of each CODECS such as JPEG, MPEG-2, 4 and H.264 standard
Date of Conference: 21-24 May 2006
Date Added to IEEE Xplore: 11 September 2006
Print ISBN:0-7803-9389-9