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Minimization of I/O Delay in the architectural synthesis of DSP data flow graphs | IEEE Conference Publication | IEEE Xplore

Minimization of I/O Delay in the architectural synthesis of DSP data flow graphs


Abstract:

This paper presents a new technique for the minimization of I/O delay in the architectural synthesis of cyclic data flow graphs (DFG) representing DSP algorithms taking i...Show More

Abstract:

This paper presents a new technique for the minimization of I/O delay in the architectural synthesis of cyclic data flow graphs (DFG) representing DSP algorithms taking into consideration the inter-processor communication delays. In this paper, the question of optimizing the I/O delay without scarifying the iteration period (throughput) with non-negligible inter-processor communication overhead is addressed. The proposed technique operating on the cyclic DFG of a DSP algorithm is designed to evaluate the relative firing times of the nodes by using Floyd-Warshall’s longest path algorithm so that the inter-processor communication overhead is taken into consideration to provide an optimized time and processor schedule. Moreover, the proposed scheme is applied to well-know DSP benchmarks and seen that it is efficient in minimizing the I/O delay without scarifying the iteration period.
Date of Conference: 18-21 May 2008
Date Added to IEEE Xplore: 13 June 2008
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Conference Location: Seattle, WA, USA

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