A new methodology to include random telegraph signals (RTS) noise in circuit analysis is proposed. The aim of this methodology is to allow integrated circuit designers to study the sensitivity of their circuits to RTS noise and thus minimise the impact of it. In this work, compact models extracted from three-dimensional dasiaatomisticpsila simulations based on random doping were used. These models define 35 nm CMOS technology devices with single charge trapping at the Si-SiO₂ interface, and therefore the amplitude of RTS noise. The timing parameters of RTS noise were predicted based on the Shockley-Reed-Hall statistics. The methodology was applied to a test circuit, four-quadrant Chible multiplier as an example, under both steady-state and time-varying bias conditions. Simulation results on variability in devices (based on Monte Carlo methods) and temperature sweep are also reported.