A time-interleaved flash-SAR ADC architecture has been suggested for high speed A/D conversion. Owing to the MSBs determined by the front end flash ADC, SAR ADC completes the A/D conversion in a reduced number of cycles. Time-interleaved SAR ADCs with a commonly shared low resolution flash ADC provide a new size and power efficient high speed ADC architecture. The proposed ADC structure has been verified by developing a behavioral model of a 6-bit 1.2 GHS/s ADC. Circuit design considerations have also been discussed based on the sampling network mismatch between the flash and SAR ADCs.