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A smart frequency presetting technique for fast lock-in LC-PLL frequency synthesizer | IEEE Conference Publication | IEEE Xplore

A smart frequency presetting technique for fast lock-in LC-PLL frequency synthesizer


Abstract:

This paper proposes a smart frequency presetting technique for fast lock-in LC-PLL frequency synthesizer. The technique accurately presets the frequency of VCO with small...Show More

Abstract:

This paper proposes a smart frequency presetting technique for fast lock-in LC-PLL frequency synthesizer. The technique accurately presets the frequency of VCO with small initial frequency error and greatly reduces the lock-in time. It can automatically compensate preset frequency variation with process and temperature. A 2.4GHz synthesizer with 1MHz reference input was implemented in 0.35µm CMOS process. The chip core area is 0.4mm2. Output frequency of VCO ranges from 2390 to 2600MHz. The measured results show that the typical lock-in time is 3µs. The phase noise is -112dBc/Hz at 600KHz offset from center frequency. The test chip consumes current of 22mA that includes the consumption of the I/O buffers.
Date of Conference: 24-27 May 2009
Date Added to IEEE Xplore: 26 June 2009
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Conference Location: Taipei, Taiwan

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