Read only memories (ROMs) occupy 40% to 80% of the area in most of the current generation system on chips (SoCs). Hence, any reduction in ROM area could effectively result in chips with low die area. A novel optimized ROM structure based on data contents is proposed in this paper. Customized address decoder and memory core are designed based on data contents leading to an area reduction of up-to 60% and considerable reduction in power and access times. Analysis of overall transistor count is performed for a few real-life SoC applications and also for random data.