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Optimization of clock-gating structures for low-leakage high-performance applications | IEEE Conference Publication | IEEE Xplore

Optimization of clock-gating structures for low-leakage high-performance applications


Abstract:

Clock Gating (CG) is a well known technique to reduce dynamic power consumption by stopping the clock to avoid unnecessary transitions in synchronous circuits. The abilit...Show More

Abstract:

Clock Gating (CG) is a well known technique to reduce dynamic power consumption by stopping the clock to avoid unnecessary transitions in synchronous circuits. The abilities of different CG-styles to save power at a flip-flop level, depending on the input activity, are analysed in this paper. Also, since conventional CG techniques usually do not take into account leakage power, some optimization procedures and guidelines are presented for leakage reduction. Focusing on those structures that do not need a latch to remove undesired transitions in gated clock, a leakage value of a fourth of the original one is achieved without degradation in timing performances.
Date of Conference: 30 May 2010 - 02 June 2010
Date Added to IEEE Xplore: 03 August 2010
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Conference Location: Paris, France

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