Comparator-based switched-capacitor pipelined ADC with background offset calibration | IEEE Conference Publication | IEEE Xplore

Comparator-based switched-capacitor pipelined ADC with background offset calibration


Abstract:

A background offset calibration technique for a comparator-based switched-capacitor (CBSC) circuit is proposed. The calibration circuitry employs a dynamic latch to deter...Show More

Abstract:

A background offset calibration technique for a comparator-based switched-capacitor (CBSC) circuit is proposed. The calibration circuitry employs a dynamic latch to determine an offset and an auxiliary differential input pair to cancel the offset. Since the proposed technique does not require additional auto-zeroing or offset detecting periods, it is suitable for high-speed low-power operations. A prototype 10-bit 100- MS/s pipelined CBSC ADC is designed and simulated in a 0.13μm CMOS process. Post-layout simulation results show the prototype ADC achieves 9.5 ENOB with a 25.4-MHz sinusoidal input signal and power consumption is 5.9 mW.
Date of Conference: 15-18 May 2011
Date Added to IEEE Xplore: 04 July 2011
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Conference Location: Rio de Janeiro, Brazil

References

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