This paper presents an energy-efficient VLSI architecture for 8×8 2-D DCT, which relies on a fast and precise implementation of the LLM algorithm. The energy-efficiency is achieved by using a combinational 1-D DCT block that explores the algorithm's intrinsic parallelism and the integer constant multiplications. The target throughput of 19 Mpixels/s, which is required for VGA@30fps, is achieved by applying a 4.9 MHz clock, that corresponds only to 17.5% of the maximum clock. Synthesis results for a 350 nm technology estimate total power as 6.08 mW, and core area as 2.1 mm². The proposed architecture shows to be at least 42% more energy efficient than the related work. To further investigate the efficiency on deep submicron technology nodes, synthesis for 90 nm and 45 nm were also performed.